1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a main word line driver circuit to which negative voltage is supplied in a semiconductor memory device.
2. Description of the Related Art
In order to reduce delay of a signal due to the resistance of poly-silicon used as a word line, a hierarchical word line structure, in which a word line is divided into a main word line (also referred to as a normal word line) and a sub-word line, is widely used. The hierarchical word line structure is disclosed by U.S. Pat. No. 5,416,748.
FIG. 1 is a schematic block diagram of a semiconductor memory device having a main word line driver circuit according to the prior art. The semiconductor memory device 100 comprises a command decoder 110, a row decoder 120, a main word line driver circuit 130, and a sub-word line driver circuit 190.
The command decoder 110 decodes a precharge command (PRECH CMD) and generates a precharge signal (PRECH) for precharging the main word lines to a low level, that is, a ground voltage. The row decoder 120 decodes row addresses (R—ADDR) and generates decoded row address signals (DRA1–DRAn, DRA—C1–DRA—C3).
In response to the precharge signal (PRECH) and decoded row address signals (DRA1–DRAn, DRA—C1–DRA—C3) the main word line driver circuit 130 generates main word line signals (MWE1–MWEn) which enables the main word lines, respectively. In response to the main word line signals (MWE1–MWEn), the sub-word line driver circuit 190 generates sub-word line signals (SWLs) for driving sub-word lines corresponding to the main word lines. For example, a main word line may correspond to four sub-word lines connected to memory cells (not shown).
FIG. 2 is a detailed diagram of the main word line driver circuit 130 of FIG. 1. Referring to FIG. 2, the main word line driver circuit 130 comprises a plurality of output units 141–14n and a ground voltage supply unit 150. For example, the ground voltage supply unit 150 may be commonly connected to eight output units.
The ground voltage supply unit 150 comprises three NMOS transistors 151, 152, and 153 serially connected, and the ground voltage (VSS) is connected to the source of the NMOS transistor 153. In response to the activation of the decoded row address signals (DRA—C1–DRA—C3), the ground voltage supply unit 150 supplies the ground voltage (VSS) to a node (NODE2).
The output unit 141 comprises a PMOS transistor 1411, an inverter 1412, and an NMOS transistor 1413, and a boosting voltage (VPP) is connected to the source of the PMOS transistor 1411.
First, an operation in which a first main word line signal (MWE1) is inactivated to a low level, that is, the ground voltage level (VSS), will now be described. In response to the activation of the precharge signal (PRECH), the PMOS transistor 1411 of the first output unit 141 pulls up the electric potential of the node (NODE1) to a high level, that is, the boosting voltage (VPP) level. The inverter 1412 inverts the electric potential of the node (NODEL) that is in a high level, to a low level such that a low level first main word line signal (MWE1) is generated.
Next, an operation in which the first main word line signal (MWE1) is activated to a high level, that is, the boosting voltage (VPP), will now be described. In response to the activation of the decoded row address signal (DRA1), the NMOS transistor 1413 of the first output unit 141 transfers the electric potential of the node (NODE2), which is pulled down to a low level, that is, VSS, by the ground voltage supply unit 150, to the node (NODE1). The inverter 1412 inverts the electric potential of the node (NODE1), which is pulled down to the low level, such that a high level first main word line signal (MWE1) is generated.
Since the output units 142–14n have the same elements as those of the first output unit 141, the description of the first output unit 141 can be referred to for detailed explanation of the output units 142–14n. However, the output units 142–14n generate main word line signals (MWE2–MWEn), respectively, in response to the precharge signal (PRECH) and decoded row address signals (DRA2–DRAn, DRA—C1–DRA—C3).
Recently, the voltages of control signals, that is, decoded row address signals (DRA1–DRAn, DRA—C1–DRA—C3), controlling the main word line driver circuit 130 have been lowered as semiconductor memory device have been using low supply voltages (VCC, for example, 2V or less). Accordingly, when the decoded row address signal (DRA1) is activated by a low supply voltage (VCC) and the ground voltage (VSS) is supplied to the node (NODE2) by the ground voltage supply unit 150, the gate voltage (Vgs) to the source of the NMOS transistor 1413 of the first output unit 141 may be a little higher than the threshold voltage of the NMOS transistor 1413. Therefore, the operation speed of the NMOS transistor 1413 which pulls down the node (NODEL) to a low level, that is, the ground voltage level (VSS), may be decreased. As a result, the transition speed from a low level to a high level of the main word line signal (MWE1) may be decreased.